A synchronous dynamic random access memory (SDRAM) is a semiconductor memory device which operates synchronously with an external clock and requires stabilization the semiconductor memory device by sequentially inputting external command after initial application of a driving operation voltage (VDD). Particularly, in the SDRAM, a precharge operation is very important since all operations are performed in the precharge state.
The precharge operation in a semiconductor memory device having a multi-bank structure is classified into an all-bank precharge operation in which the precharge is performed on all of the banks, and a single-bank precharge operation, in which the precharge is performed by the banks. In the all-bank precharge operation, a peak current is increased since the precharge of the banks is performed at the same time, which will be described with reference to FIG. 1 illustrating a timing diagram of operation of a conventional bank precharge signal generation circuit.
As illustrated, if an all-bank precharge signal ICAR<4> is at a high level when a pulse of a precharge signal PCGP is inputted, an all-bank precharge operation is initiated. That is to say, when the all-bank precharge signal (ICAR<4> of a high level and a precharge pulse of a high level are inputted, first through eighth bank precharge signals PCGP_BA<0:7> for precharging first through eighth banks, respectively, in a semiconductor memory device with a eight-bank structure are enabled to a high level at the same time (point X).
As such, simultaneous initiation of the precharge operation on the first through eighth banks sharply increases the peak current consumed at a time point of initiation of the all-bank precharge operation and the sharp increase in the peak current causes deterioration of noise immunity and mobile reception sensitivity.